1. Field of the Invention
The present invention relates to a manufacturing method for the SOI (an abridgement of Silicon On Insulator) substrate which is so formed that silicon wafers are bonded face to face with an insulating film therebetween, and more particularly to the manufacturing method for the SOI substrate wherein the quality of the single crystal layer thereof in which semiconductor devises are fabricated is crystallographically improved.
2. Description of the Prior Art
At the very beginning stage of development of integrated circuitry was a desire of obtaining silicon single crystal grown on an insulator substrate (hereinafter this will be referred to as SOI structure). It was the reason therefor that SOI structure has a plenty of advantages such as making miniaturization or effective isolation of elements possible, easier achievement of high reliability in the semiconductor devise performance through increase in dielectric strength, insensitiveness to soft errors and minimization of a latch-up phenomenon and realization of high frequency operation through lower parasitic interconnect capacitance.
These features of SOI structure are now increasingly more highly thought of in the current integrated circuitry technology in pursuit of further miniaturization and ever-increased packing densities, while recently the so-called power integrated circuit, which incorporates a high voltage devise(s) as part in the same silicon chip, becomes more and more popular in such electronics fields as constant-voltage power circuits for electronic automatic exchange, discharge-type printer or plasma display or automobile electronics and along this trend a new SOI structure has become required that a thicker silicon single crystal layer of, for example 5 .mu.m.about.50 .mu.m thick is formed on the insulator substrate.
For isolation in power integrated circuits the pn junction does not work properly in regard to peak inverse voltage and in addition Joule heating, increase in the leakage current due to the heating and other unstable phenomena are not avoided without the use of SiO.sub.2 isolation.
Conventionally there was known a method to realize SOI structure that silicon single crystal is directly grown by the vapor growth technique on a single crystal insulator substrate, for example a sapphire substrate, by which the silicon single crystal with crystallographically good quality is not obtained. The method, therefore, can not be said to have succeeded in the sense of practicality. There is also known another technology attracting public attention that oxygen ions are implanted into the surface region of a single crystal wafer and thus a buried oxide layer is formed in bulk across the full wafer (This technology is called SIMOX or Separation by Implanted Oxygen). This technology has problems that the quality of the buried oxide layer and the crystallographic quality of the surface region is not satisfactory and the surface region is poor in dielectric strength due to the poor crystallographic quality, which means there will be still a long way to put it to practical use.
In addition to the manufacturing technologies of the above-mentioned SOI structure, there is still another method that attract keener public attention as being put faster to practical use which includes the method according to the present invention in the technological category, where silicon wafers are directly bonded each other with an SiO.sub.2 film sandwiched therebetween. In the men, hod, SOI substrate has as a constituent a single crystal with a good quality from the Czochralski method to fabricate semiconductor devises therein and the sandwiched SiO.sub.2 film is formed by thermal oxidation, which dielectric strength is generally admitted to be good enough for practical use.
With respect to the SOI substrate made by a conventional technique, the, present inventors have found a problem left unsolved that a plenty of microdefects or mainly oxidation induced stacking faults (herein after referred to as OSF), which originate from deposition of interstitial oxygen atoms, are generated in the bulk of single crystal silicon used for fabricating semiconductor devises (hereinafter SOI layer), when the SOI layer is thick, for example 20 .mu.m to 30 .mu.m or more in thickness, though there is no such problem as mentioned above for the SOI layer having a thickness under about 2 .mu.m. Consequently, it was naturally expected that a big technical problem would arise in the application of SOI structure with a thick SOI layer to the above-mentioned power integrated circuit, since miniaturized elements in an integrated circuit might adversely be affected in performance by power devises incorporated in the same chip.